1. Field of the Invention
This invention relates in general to semiconductor devices and more specifically to packaging semiconductor devices.
2. Description of the Related Art
Integrated circuit dies may be implemented in packaged integrated circuits for the protection of the die. In some examples, integrated circuit die or dies are placed on one side of a substrate with conductive interconnecting structures that electrically couple the die bond pads to external conductors (e.g. bond pads, solder balls) on the other side of the substrate.
In other examples, multiple singulated die may be encapsulated in a group package where the bond pads of the die are exposed on one side of the group package. An interconnect layer including conductive vias, interconnects, and interlayer dielectric material may be subsequently formed on the side of the exposed die pads wherein external conductors (e.g. balls, pads) may be formed on top of the interconnects, with the external conductors electrically coupled to the die bond pads. The resultant structure is then singulated into separated packaged integrated circuits.
One problem with the above technique is that locating the die accurately with the group package may be difficult due to encapsulant flow, cure shrinkage, and accuracy of the placement equipment. Inaccuracies in the die placement within the encapsulant make subsequent formation of the overlying interconnects difficult and may reduce yield.
What is needed is an improved technique for packaged integrated circuit formation.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The Figures are not necessarily drawn to scale.